Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design

Mingoo Seok, Dongsuk Jeon, Chaitali Chakrabarti, David Blaauw, Dennis Sylvester

Research output: Chapter in Book/Report/Conference proceedingConference contribution

25 Scopus citations


This paper investigates pipelining methodologies for the ultra low voltage regime. Based on an analytical model and simulations, we propose a pipelining technique that provides higher energy efficiency and performance than conventional approaches to ultra low voltage design. Two-phase latch based design and sequential circuit optimizations are also proposed to further improve energy efficiency and performance. Silicon results demonstrate a 16b multiplier using the approaches in 65nm CMOS improve energy efficiency by 30% and performance by 60%.

Original languageEnglish (US)
Title of host publication2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)9781450306362
StatePublished - 2011

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


  • Pipeline
  • Super-pipeline
  • Ultra Low Power
  • Ultra Low Voltage

ASJC Scopus subject areas

  • Computer Science Applications
  • Modeling and Simulation
  • Control and Systems Engineering
  • Electrical and Electronic Engineering


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