Abstract
Parasitic-aware synthesis and optimization techniques are presented for a 0.35μm CMOS three-stage 1W 900MHz class-E power amplifier. Employing bond wire and spiral inductors, it achieves 25dB gain with 49% drain efficiency from a 3.3V supply. Simulated annealing optimization is used taking advantage of its ability to escape local minima.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Symposium on Circuits and Systems |
Volume | 1 |
State | Published - 2002 |
Event | 2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002 |
Other
Other | 2002 IEEE International Symposium on Circuits and Systems |
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Country/Territory | United States |
City | Phoenix, AZ |
Period | 5/26/02 → 5/29/02 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials