Parallel high throughput soft-output sphere decoder

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


Multiple-Input-Multiple-Output communication systems demand fast sphere decoding with high performance. We propose a high throughput soft-output fixed complexity sphere decoder (PFSD) that is parallel and has comparable performance to list fixed complexity sphere decoder (LFSD) and K-best sphere decoder. In addition, we propose a parallel QR decomposition algorithm to lower the preprocessing overhead, and a low complexity LLR algorithm to allow parallel update of LLR values. We demonstrate the BER and computation complexity advantages of the PFSD algorithm in a 4x4 16-QAM system. The PFSD algorithm has been mapped onto Xilinx XC4VLX160 FPGA. The resulting PFSD decoder can produce 8 candidate vectors per clock cycle, and achieve upto 75Mbps throughput for 4x4 64-QAM configuration at 100MHz with low control overhead.

Original languageEnglish (US)
Title of host publication2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - Proceedings
Number of pages6
StatePublished - Dec 27 2010
Event2010 IEEE Workshop on Signal Processing Systems, SiPS 2010 - San Francisco, CA, United States
Duration: Oct 6 2010Oct 8 2010

Publication series

NameIEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation
ISSN (Print)1520-6130


Other2010 IEEE Workshop on Signal Processing Systems, SiPS 2010
Country/TerritoryUnited States
CitySan Francisco, CA


  • FPGA
  • Parallel implementation
  • Sphere decoding

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Signal Processing
  • Applied Mathematics
  • Hardware and Architecture


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