OTA-free 1-1 MASH ADC using Fully Passive Noise Shaping SAR VCO ADC

Sanjeev Tannirkulam Chandrasekaran, Sumukh P. Bhanushali, Stefano Pietri, Arindam Sanyal

Research output: Chapter in Book/Report/Conference proceedingConference contribution


We present an OTA-free 1-1 MASH ADC utilizing a fully passive noise shaping (FPNS) SAR as first-stage and open-loop VCO ADC as second stage. The key contribution of this work is to address the challenge of driving large sampling capacitor for high resolution NS-SAR. The proposed architecture reduces resolution of SAR stage and leverages residue attenuation due to passive charge sharing in the FPNS SAR to linearize the VCO. Combining an FPNS SAR with a VCO ADC shapes in-band thermal noise of VCO and SAR comparator at ADC output. Additionally, we demonstrate a computationally inexpensive foreground inter-stage gain calibration algorithm for the proposed ADC architecture. The prototype ADC consumes 0.16mW while achieving an SNDR/DR of 71.5/75.8dB over a 1.1MHz bandwidth and walden FoM of 23.3fJ/step which is the lowest in 65nm technology.

Original languageEnglish (US)
Title of host publication2021 Symposium on VLSI Circuits, VLSI Circuits 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487796
StatePublished - Jun 13 2021
Externally publishedYes
Event35th Symposium on VLSI Circuits, VLSI Circuits 2021 - Virutal, Online
Duration: Jun 13 2021Jun 19 2021

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Conference35th Symposium on VLSI Circuits, VLSI Circuits 2021
CityVirutal, Online


  • inter-stage gain calibration and MASH
  • noise-shaping SAR
  • oversampling ADC
  • ring VCO

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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