On-chip interconnect modeling technologies

E. Aykut Dengi; Ronald A. Rohrer

On-chip interconnect modeling technologies

E. Aykut Dengi, Ronald A. Rohrer

Arizona State University

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Developing a compact model for an interconnect is important to render consistent interconnect models at different levels of the design hierarchy and achieve design convergence. This development requires on-chip modeling technologies for post-layout verification, called `parasitic extraction', and characterization/silicon-correlation which is important to interconnect modeling at all levels.

Original language	English (US)
Number of pages	1
State	Published - Dec 1 1997
Event	Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging - San Jose, CA, USA Duration: Oct 27 1997 → Oct 29 1997

Other

Other	Proceedings of the 1997 6th Topical Meeting on Electrical Performance of Electronic Packaging
City	San Jose, CA, USA
Period	10/27/97 → 10/29/97

ASJC Scopus subject areas

General Engineering

Cite this

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title = "On-chip interconnect modeling technologies",

abstract = "On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Developing a compact model for an interconnect is important to render consistent interconnect models at different levels of the design hierarchy and achieve design convergence. This development requires on-chip modeling technologies for post-layout verification, called `parasitic extraction', and characterization/silicon-correlation which is important to interconnect modeling at all levels.",

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year = "1997",

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AU - Rohrer, Ronald A.

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AB - On-chip interconnect must be accounted for at all levels of the design hierarchy, starting with synthesis, through physical design and ending with verification. Developing a compact model for an interconnect is important to render consistent interconnect models at different levels of the design hierarchy and achieve design convergence. This development requires on-chip modeling technologies for post-layout verification, called `parasitic extraction', and characterization/silicon-correlation which is important to interconnect modeling at all levels.

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M3 - Paper

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Y2 - 27 October 1997 through 29 October 1997

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On-chip interconnect modeling technologies

Abstract

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ASJC Scopus subject areas

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