Novel first-level interconnect techniques for flip chip on MEMS devices

Jemmy Sutanto, Sindhu Anand, Chetan Patel, Jitendran Muthuswamy

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


Flip-chip packaging is desirable for microelectromechanical systems (MEMS) devices because it reduces the overall package size and allows scaling up the number of MEMS chips through 3-D stacks. In this report, we demonstrate three novel techniques to create first-level interconnect (FLI) on MEMS: 1) Dip and attach technology for Ag epoxy; 2) Dispense technology for solder paste; 3) Dispense, pull, and attach technology (DPAT) for solder paste. The above techniques required no additional microfabrication steps, produced no visible surface contamination on the MEMS active structures, and generated high-aspect-ratio interconnects. The developed FLIs were successfully tested on MEMS moveable microelectrodes microfabricated by SUMMiTV \rm TM process producing no apparent detrimental effect due to outgassing. The bumping processes were successfully applied on Al-deposited bond pads of 100 μm × 100 μm with an average bump height of 101.3 μm for Ag and 184.8 μm for solder (63Sn, 37Pb). DPAT for solder paste produced bumps with the aspect ratio of 1.8 or more. The average shear strengths of Ag and solder bumps were 78 MPa and 689 kPa, respectively. The electrical test on Ag bumps at 794 A/cm 2 demonstrated reliable electrical interconnects with negligible resistance. These scalable FLI technologies are potentially useful for MEMS flip-chip packaging and 3-D stacking.

Original languageEnglish (US)
Article number6069517
Pages (from-to)132-144
Number of pages13
JournalJournal of Microelectromechanical Systems
Issue number1
StatePublished - Feb 2012


  • 3-D stacks
  • BioMEMS
  • flip chip
  • flux contamination
  • interconnects
  • microchip
  • packaging
  • solder

ASJC Scopus subject areas

  • Mechanical Engineering
  • Electrical and Electronic Engineering


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