Neural processing of semantic networks

L. C. Shiue, R. O. Grondin

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Scopus citations


    Summary form only given, as follows. A dynamically reconfigurable architecture for parallel processing of semantic networks is described. The proposed architecture is made up of a network of Boolean McCulloch-Pitts neuron-like cells, each dedicated to one vertex of a semantic network and its associated edges. By partitioning each cell and integrating the neural-like network into several functional blocks, a highly regularly structured reconfigurable processing unit is achievable. Such a processing unit is capable of storing symbolic assertions and performing parallel search and deduction within its collection of knowledge. Potentially this architecture can be realized by the VLSI technology, and the design approach also exploits an application for on-chip expert systems.

    Original languageEnglish (US)
    Title of host publicationIJCNN Int Jt Conf Neural Network
    Editors Anon
    Place of PublicationPiscataway, NJ, United States
    PublisherPubl by IEEE
    Number of pages1
    StatePublished - 1989
    EventIJCNN International Joint Conference on Neural Networks - Washington, DC, USA
    Duration: Jun 18 1989Jun 22 1989


    OtherIJCNN International Joint Conference on Neural Networks
    CityWashington, DC, USA

    ASJC Scopus subject areas

    • General Engineering


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