Multilevel reliability simulation for IC design

Ketul B. Sutaria, Jyothi B. Velamala, Venkatesa Ravi, Gilson Wirth, Takashi Sato, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Scopus citations


With CMOS technology scaling, design for reliability becomes a vitally important part in today's design cycle. Aging mechanisms, such as NBTI and CHC, degrade the performance of a circuit over time, eventually causing system functional failure. NBTI predominantly affects digital circuits, inducing delay shift in logic paths and data instability in memory cells, while CHC impacts the mismatch, gain, and offset in analog/mixed signal (AMS) circuits. Accurate long-term modeling of these aging effects is key to circuit failure analysis. In addition, simulation efficiency is critical to reliability diagnosis in a modern design at the scale of multi-million gates. This chapter presents a new simulation flow that integrates long-term aging models, which are sensitive to dynamic voltage scaling and switching activities, with aging-aware standard cell library, predicting the degradation for both digital and AMS circuits. Different from conventional reliability tools that rely on extrapolation for long-term aging prediction, the new methodology continuously monitors the shift in operating conditions and circuit performance metrics toward the end of the lifetime. As implemented into representative VLSI design tools, the newly developed aging models and tools dramatically improve simulation efficiency and accuracy, supporting design practice for reliability with scaled CMOS technology.

Original languageEnglish (US)
Title of host publicationBias Temperature Instability for Devices and Circuits
PublisherSpringer New York
Number of pages31
ISBN (Print)9781461479093, 1461479088, 9781461479086
StatePublished - Jul 1 2014

ASJC Scopus subject areas

  • General Engineering


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