TY - JOUR
T1 - Multi-module multi-port memory design for low power embedded systems
AU - Shiue, Wen Tsong
AU - Chakrabarti, Chaitali
N1 - Funding Information:
This work was supported by the NSF/S/IUCRC Center for Low Power Electronics (EEC-9523338), that is jointly funded by the National Science Foundation, the State of Arizona and the member companies.
PY - 2005/7
Y1 - 2005/7
N2 - In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.
AB - In this paper we describe a multi-module, multi-port memory design procedure that satisfies area and/or energy constraints for embedded applications. Our procedure consists of application of loop transformations and reordering of array accesses to reduce the memory bandwidth followed by memory allocation and assignment procedures based on ILP models and heuristic-based algorithms. The specific problems include determination of (a) the memory configuration with minimum area, given the energy bound, (b) the memory configuration with minimum energy, given the area bound, (c) array allocation such that the energy consumption is minimum for a given memory configuration (number of modules, size and number of ports per module). The results obtained by the heuristics match well with those obtained by the ILP methods.
KW - ILP models
KW - Memory allocation and assignment
KW - Multi-module memory
KW - Multi-port memory
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U2 - 10.1007/s10617-005-1195-3
DO - 10.1007/s10617-005-1195-3
M3 - Article
AN - SCOPUS:23944504935
SN - 0929-5585
VL - 9
SP - 235
EP - 261
JO - Design Automation for Embedded Systems
JF - Design Automation for Embedded Systems
IS - 4
ER -