Methods for designing low-leakage ESD power supply clamps

Timothy J. Maloney, Steven S. Poon, Lawrence T. Clark

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


Low-power semiconductor components require minimizing leakage currents including those from ESD protection circuits. Here, MOSFET ESD power clamps with substantial leakage reduction over previous approaches are presented. Designs are described for core logic circuits and for I/O applications where supply voltages exceed what single gate oxides can reliably sustain.

Original languageEnglish (US)
Pages (from-to)85-97
Number of pages13
JournalJournal of Electrostatics
Issue number2-3 SPEC. ISS.
StatePublished - Oct 1 2004


  • Back gate bias
  • ESD protection
  • Electrostatic discharge
  • IC design for reliability
  • Low leakage
  • PMOS
  • Power clamp
  • RC trigger

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Biotechnology
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


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