TY - GEN
T1 - Measurements and Simulation of Self-Heating in 40 nm SOI MOSFETs
AU - Zhang, Xiong
AU - Mehr, Payam
AU - Vasileska, Dragica
AU - Thornton, Trevor
N1 - Publisher Copyright:
© 2021 IEEE.
PY - 2021/4/8
Y1 - 2021/4/8
N2 - To understand self-heating in SOI CMOS, conventional and trap-rich substrates are used to fabricate 40nm gate length NFET pairs that share the same active region. One NFET serves as a heater, while the other is used as a calibrated thermometer. Measurements of the local heating confirm the simulated temperature distribution. Heat flow out of the metal contacts reduces the self-heating in NFETs on trap-rich substrates which have reduced thermal conductivity compared to conventional SOI wafers.
AB - To understand self-heating in SOI CMOS, conventional and trap-rich substrates are used to fabricate 40nm gate length NFET pairs that share the same active region. One NFET serves as a heater, while the other is used as a calibrated thermometer. Measurements of the local heating confirm the simulated temperature distribution. Heat flow out of the metal contacts reduces the self-heating in NFETs on trap-rich substrates which have reduced thermal conductivity compared to conventional SOI wafers.
KW - CMOS
KW - Self-heating effect (SHE)
KW - modeling and simulation
KW - silicon-on-insulator (SOI)
UR - http://www.scopus.com/inward/record.url?scp=85106505933&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85106505933&partnerID=8YFLogxK
U2 - 10.1109/EDTM50988.2021.9421023
DO - 10.1109/EDTM50988.2021.9421023
M3 - Conference contribution
AN - SCOPUS:85106505933
T3 - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
BT - 2021 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2021
Y2 - 8 April 2021 through 11 April 2021
ER -