@inproceedings{1623fc475fe94d3d9c09d1edc75752ec,
title = "Managing standby and active mode leakage power in deep sub-micron design",
abstract = "Scaling has allowed rising transistor counts per die and increases leakage at an exponential rate, making power a primary constraint in all integrated circuit designs. Future designs must address emerging leakage components due to direct band to band tunneling, through MOSFET oxides and at steep junction doping gradients. In this paper, we describe circuit design techniques for managing leakage power, both during standby and for limiting the leakage power contribution during active operation. The efficacy, design effort, and process ramifications of different approaches are examined. The schemes are primarily aimed at hand-held devices such as cell phones, since the needs for low power are most acute in these markets due to limited battery capacity.",
keywords = "Battery lifetime, Drowsy mode, MTCMOS, SRAM leakage control, TGSRAM, Thick gate shadow latch, Transistor leakage",
author = "Clark, {Lawrence T.} and Rakesh Patel and Beatty, {Timothy S.}",
year = "2004",
doi = "10.1145/1013235.1013239",
language = "English (US)",
isbn = "1581139292",
series = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04",
publisher = "Association for Computing Machinery",
pages = "274--279",
booktitle = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04",
note = "Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04 ; Conference date: 09-08-2004 Through 11-08-2004",
}