Low standby power and robust FinFET based SRAM design

Behzad Ebrahimi, Saeed Zeinolabedmzadeh, Ali Afzali-Kusha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Scopus citations

Abstract

In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the V t-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power consumption. To assess the efficiency of the approach, HSPICE simulations in 45nm and 32nm FinFET technologies are used. The results show considerable improvements in terms of the standby power as well as the hold and read SNM. This suggests that the Vt-control method may be used for realizing low-standby power and robust SRAM.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationTrends in VLSI Technology and Design, ISVLSI 2008
Pages185-190
Number of pages6
DOIs
StatePublished - Sep 22 2008
Externally publishedYes
EventIEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 - Montpellier, France
Duration: Apr 7 2008Apr 9 2008

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Conference

ConferenceIEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008
Country/TerritoryFrance
CityMontpellier
Period4/7/084/9/08

Keywords

  • FinFET
  • Low-power memory
  • SRAM
  • Standby power
  • Static noise margin
  • V-control method

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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