Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun

Research output: Contribution to journalArticlepeer-review

22 Scopus citations


This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

Original languageEnglish (US)
Pages (from-to)2249-2262
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number6
StatePublished - Jun 1 2022


  • Analog-to-digital converter (ADC)
  • energy efficiency
  • low power
  • successive approximation register (SAR)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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