An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners and temperature with appropriate body bias selection. DDC technology also increases SRAM static noise margin (SNM) reduces 8Mb VDDmin by 150 mV reduces SRAM active leakage by 50% while maintaining Iread and reduces SRAM retention leakage by 5x.
|Title of host publication
|Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
|Institute of Electrical and Electronics Engineers Inc.
|Published - Nov 7 2013
|35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: Sep 22 2013 → Sep 25 2013
|Proceedings of the Custom Integrated Circuits Conference
|35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
|San Jose, CA
|9/22/13 → 9/25/13
ASJC Scopus subject areas
- Electrical and Electronic Engineering