Linear-programming-based techniques for synthesis of network-on-chip architectures

Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod

Research output: Contribution to journalArticlepeer-review

216 Scopus citations


Application-specific system-on-chip (SoC) design offers the opportunity for incorporating custom network-on-chip (NoC) architectures that are more suitable for a particular application, and do not necessarily conform to regular topologies. This paper presents novel mixed integer linear programming (MILP) formulations for synthesis of custom NoC architectures. The optimization objective of the techniques is to minimize the power consumption subject to the performance constraints. We present a two-stage approach for solving the custom NoC synthesis problem. The power consumption of the NoC architecture is determined by both the physical links and routers. The power consumption of a physical link is dependent upon the length of the link, which in turn, is governed by the layout of the SoC. Therefore, in the first stage, we address the floorplanning problem that determines the locations of the various cores and the routers. In the second stage, we utilize the floorplan from the first stage to generate topology of the NoC and the routes for the various traffic traces. We also present a clustering-based heuristic technique for the second stage to reduce the run times of the MILP formulation. We analyze the quality of the results and solution times of the proposed techniques by extensive experimentation with realistic benchmarks and comparisons with regular mesh-based NoC architectures.

Original languageEnglish (US)
Article number1637470
Pages (from-to)407-420
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
StatePublished - Apr 2006


  • Design automation
  • Integrated circuit interconnection
  • Multiprocessor interconnection

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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