"It's a small world after all": NoC performance optimization via long-range link insertion

Umit Y. Ogras, Radu Marculescu

Research output: Contribution to journalArticlepeer-review

358 Scopus citations


Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.

Original languageEnglish (US)
Article number1661619
Pages (from-to)693-706
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number7
StatePublished - Jul 2006
Externally publishedYes


  • Design automation
  • Multiprocessor system-on-chip (MP-SoC)
  • Network-on-chip (NoC)
  • Performance analysis

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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