Investigation of power delay trade-offs for dual Vt CMOS circuits

Research output: Chapter in Book/Report/Conference proceedingChapter

10 Scopus citations


The availability of dual Vt CMOS process provides a practical way to achieve high performance and low leakage power dissipation for current deep submicron technology. Early work on leakage power optimization of digital circuits utilizing dual Vt devices show some promising results. However, due to the lack of real dual Vt process models and parameters, these works are based on simple power and delay analysis of dual Vt devices. For example, the impact of dual Vt on the short circuit power dissipation is ignored in all these works. In this paper we provide extensive HSPICE simulation results on CMOS gates and circuits from a commercial dual Vt CMOS process. The experimental results show that optimization of dual Vt circuits involves complex trade-offs between leakage power, short circuit power and performance. For example, it is observed that using lower Vt devices does not always result in a faster circuit. One of the main contributions of this paper is that it reveals some new challenges and opportunities offered by the dual Vt technology to both circuits designers and CAD software developers for circuit optimization.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
Place of PublicationPiscataway, NJ, United States
Number of pages7
StatePublished - 1999
Externally publishedYes
EventInternational Conference on Computer Design (ICCD'99) - Austin, TX, USA
Duration: Oct 10 1999Oct 13 1999


OtherInternational Conference on Computer Design (ICCD'99)
CityAustin, TX, USA

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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