TY - GEN
T1 - Integration of threshold logic gates with RRAM devices for energy efficient and robust operation
AU - Yang, Jinghua
AU - Kulkarni, Niranjan
AU - Yu, Shimeng
AU - Vrudhula, Sarma
PY - 2014
Y1 - 2014
N2 - Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.
AB - Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.
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U2 - 10.1109/NANOARCH.2014.6880500
DO - 10.1109/NANOARCH.2014.6880500
M3 - Conference contribution
AN - SCOPUS:84906734726
SN - 9781479963836
T3 - Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014
SP - 39
EP - 44
BT - Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014
PB - IEEE Computer Society
T2 - 2014 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2014
Y2 - 8 July 2014 through 10 July 2014
ER -