TY - GEN
T1 - HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector
AU - Chen, Hong Yu
AU - Yu, Shimeng
AU - Gao, Bin
AU - Huang, Peng
AU - Kang, Jinfeng
AU - Wong, H. S.Philip
N1 - Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2012
Y1 - 2012
N2 - Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50μA), switching speed (∼50ns), switching endurance (>108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125 oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large Ron (∼100k) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.
AB - Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50μA), switching speed (∼50ns), switching endurance (>108 cycles), half-selected read disturbance immunity (>109 cycles), retention (>105s @125 oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture. Analysis shows that for such 3D selector-less array, a large Ron (∼100k) from the non-linear I-V helps reduce the sneak path current, and a low interconnect resistance using metal planes as word lines reduces the undesirable voltage drop on the interconnect. As a conservative estimate, simulation shows that Mb-scale array without cell selector is achievable.
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U2 - 10.1109/IEDM.2012.6479083
DO - 10.1109/IEDM.2012.6479083
M3 - Conference contribution
AN - SCOPUS:84876142491
SN - 9781467348706
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 20.7.1-20.7.4
BT - 2012 IEEE International Electron Devices Meeting, IEDM 2012
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2012 IEEE International Electron Devices Meeting, IEDM 2012
Y2 - 10 December 2012 through 13 December 2012
ER -