Folded Source-Coupled Logic vs. CMOS Static Logic for Low-Noise Mixed-Signal ICs

David J. Allstot, San Hwa Chee, Sayfe Kiaei, Manu Shrivastawa

Research output: Contribution to journalArticlepeer-review

89 Scopus citations


CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (ΔVL ≌ 0.2Fdd)than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30–300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-rim CMOS process, and simulated results with a standard 1-rim process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 33- and 2.0-V power supplies.

Original languageEnglish (US)
Pages (from-to)553-563
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
Issue number9
StatePublished - Sep 1993
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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