TY - GEN
T1 - Fast and scalable priority encoding using static CMOS
AU - Maurya, Satendra Kumar
AU - Clark, Lawrence T.
PY - 2010/8/31
Y1 - 2010/8/31
N2 - The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases with the number of priority encoder bits, with a delay improvement of 41.2% for a 16 inputs design.
AB - The design of high speed, compact and low power priority encoder circuits using static CMOS gates is presented. The proposed hierarchical static design has improved delay and power compared to a dynamic domino circuit implementation. For an 8-bit priority encoder design the proposed approach shows 77.1% power dissipation, 63.6% transistor count and 36% delay improvement. The improvement increases with the number of priority encoder bits, with a delay improvement of 41.2% for a 16 inputs design.
UR - http://www.scopus.com/inward/record.url?scp=77956009321&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77956009321&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2010.5537688
DO - 10.1109/ISCAS.2010.5537688
M3 - Conference contribution
AN - SCOPUS:77956009321
SN - 9781424453085
T3 - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
SP - 433
EP - 436
BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems
T2 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
Y2 - 30 May 2010 through 2 June 2010
ER -