TY - GEN
T1 - Exploration of Memory and Cluster Modes in Directory-Based Many-Core CMPs
AU - Charles, Subodha
AU - Patil, Chetan Arvind
AU - Ogras, Umit Y.
AU - Mishra, Prabhat
N1 - Funding Information:
This work was partially supported by the National Science Foundation (NSF) grants CNS-1526687 and CNS-1526562.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/10/26
Y1 - 2018/10/26
N2 - Networks-on-chip have become the standard interconnect solution to address the communication requirements of many-core chip multiprocessors. It is well-known that network performance and power consumption depend critically on the traffic load. The network traffic itself is a function of not only the application, but also the cache coherence protocol, and memory controller/directory locations. Communication between the distributed directory to memory can introduce hotspots, since the number of memory controllers is much smaller than the number of cores. Therefore, it is critical to account for directorymemory communication, and model them accurately in architecture simulators. This paper analyzes the impact of directorymemory traffic and different memory and cluster modes on the NoC traffic and system performance. We demonstrate that unrealistic models in a widely used multiprocessor simulator produce misleading power and performance predictions. Finally, we evaluate different memory and cluster modes supported by Intel Xeon-Phi processors, and validate our models on four different cache coherence protocols.
AB - Networks-on-chip have become the standard interconnect solution to address the communication requirements of many-core chip multiprocessors. It is well-known that network performance and power consumption depend critically on the traffic load. The network traffic itself is a function of not only the application, but also the cache coherence protocol, and memory controller/directory locations. Communication between the distributed directory to memory can introduce hotspots, since the number of memory controllers is much smaller than the number of cores. Therefore, it is critical to account for directorymemory communication, and model them accurately in architecture simulators. This paper analyzes the impact of directorymemory traffic and different memory and cluster modes on the NoC traffic and system performance. We demonstrate that unrealistic models in a widely used multiprocessor simulator produce misleading power and performance predictions. Finally, we evaluate different memory and cluster modes supported by Intel Xeon-Phi processors, and validate our models on four different cache coherence protocols.
UR - http://www.scopus.com/inward/record.url?scp=85057334595&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85057334595&partnerID=8YFLogxK
U2 - 10.1109/NOCS.2018.8512154
DO - 10.1109/NOCS.2018.8512154
M3 - Conference contribution
AN - SCOPUS:85057334595
T3 - 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
BT - 2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018
Y2 - 4 October 2018 through 5 October 2018
ER -