Energy and Performance Benchmarking of a Domain Wall-Magnetic Tunnel Junction Multibit Adder

T. Patrick Xiao, Matthew J. Marinella, Christopher H. Bennett, Xuan Hu, Ben Feinberg, Robin Jacobs-Gedrim, Sapan Agarwal, John S. Brunhaver, Joseph S. Friedman, Jean Anne C. Incorvia

Research output: Contribution to journalArticlepeer-review

17 Scopus citations


The domain-wall (DW)-magnetic tunnel junction (MTJ) device implements universal Boolean logic in a manner that is naturally compact and cascadable. However, an evaluation of the energy efficiency of this emerging technology for standard logic applications is still lacking. In this article, we use a previously developed compact model to construct and benchmark a 32-bit adder entirely from DW-MTJ devices that communicates with DW-MTJ registers. The results of this large-scale design and simulation indicate that while the energy cost of systems driven by spin-Transfer torque (STT) DW motion is significantly higher than previously predicted, the same concept using spin-orbit torque (SOT) switching benefits from an improvement in the energy per operation by multiple orders of magnitude, attaining competitive energy values relative to a comparable CMOS subprocessor component. This result clarifies the path toward practical implementations of an all-magnetic processor system.

Original languageEnglish (US)
Article number8910439
Pages (from-to)188-196
Number of pages9
JournalIEEE Journal on Exploratory Solid-State Computational Devices and Circuits
Issue number2
StatePublished - Dec 2019


  • Benchmarking
  • domain wall (DW)
  • magnetic logic
  • magnetic tunnel junction (MTJ)
  • post-CMOS logic
  • spintronics

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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