TY - JOUR

T1 - Efficient symbolic algorithms for computing the minimum and bounded leakage states

AU - Chopra, Kaviraj

AU - Vrudhula, Sarma

N1 - Funding Information:
Manuscript received June 16, 2004; revised March 23, 2005 and November 25, 2005. This work was supported in part by the National Science Foundation (NSF) Center for Low Power Electronics (CLPE) under Grant EC-9523338 and NSF ITR Grant CR-0205227. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation. This paper was recommended by Associate Editor L. Stok.

PY - 2006/12

Y1 - 2006/12

N2 - Static power consumption due to subthreshold, gate, and junction leakages has become a significant component of the total power consumption. For nanoscale circuits, leakage poses one of the most important challenges to the continuation of Moore's law. The leakage of a logic gate varies by an order of magnitude over its Boolean input space. Thus, one way to minimize leakage in a circuit during standby mode is to apply an input vector for which the leakage is at its minimum. Such a set of vectors is called the minimum leakage set (MLS). In this paper, an efficient algorithm for computing the exact MLS is presented. The approach is based on implicit enumeration using integer-valued decision diagrams. Since the search space for MLS is exponential in the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. Next, the problem of the increased switching power, which results from driving all inputs to a given state when entering the standby mode, is addressed. For a given upper bound B on the leakage, the MLS algorithm is extended to identify the maximal input cube with the minimum switching cost from the set of minterms whose maximum leakage is ≤ B. The switching cost associated with an input is taken to be proportional to the load capacitance of that input. The algorithms have been successfully tested on the ISCAS85 and MCNC91 benchmark circuits.

AB - Static power consumption due to subthreshold, gate, and junction leakages has become a significant component of the total power consumption. For nanoscale circuits, leakage poses one of the most important challenges to the continuation of Moore's law. The leakage of a logic gate varies by an order of magnitude over its Boolean input space. Thus, one way to minimize leakage in a circuit during standby mode is to apply an input vector for which the leakage is at its minimum. Such a set of vectors is called the minimum leakage set (MLS). In this paper, an efficient algorithm for computing the exact MLS is presented. The approach is based on implicit enumeration using integer-valued decision diagrams. Since the search space for MLS is exponential in the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. Next, the problem of the increased switching power, which results from driving all inputs to a given state when entering the standby mode, is addressed. For a given upper bound B on the leakage, the MLS algorithm is extended to identify the maximal input cube with the minimum switching cost from the set of minterms whose maximum leakage is ≤ B. The switching cost associated with an input is taken to be proportional to the load capacitance of that input. The algorithms have been successfully tested on the ISCAS85 and MCNC91 benchmark circuits.

KW - Decision diagrams

KW - Leakage power analysis

KW - Power minimization

KW - Symbolic techniques

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U2 - 10.1109/TCAD.2006.882603

DO - 10.1109/TCAD.2006.882603

M3 - Article

AN - SCOPUS:33845636183

SN - 0278-0070

VL - 25

SP - 2820

EP - 2832

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 12

ER -