TY - GEN
T1 - Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints
AU - Ghosh, Pavel
AU - Sen, Arunabha
PY - 2010
Y1 - 2010
N2 - Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (PEs). This reduction in energy consumption comes at the cost of the energy consumption of the level shifters between voltage islands. Moreover, from physical design perspective it is desirable to have a limited number of voltage islands. Considering voltage islanding during mapping of the PEs to the NoC routers can significantly reduce both the computational and the level-shifter energy consumptions and the communication energy consumption on the NoC links. In this paper, we formulate the problem as an optimization problem with an objective of minimizing the overall energy consumption constrained by the performance in terms of delay and the maximum number of voltage islands. We provide the optimal solution to our problem using Mixed Integer Linear Program (MILP) formulation. We also propose a heuristic based on random greedy selection to solve the problem. Experimental results using E3S benchmark applications and some real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.
AB - Voltage islanding technique in Network-on-Chip (NoC) can significantly reduce the computational energy consumption by scaling down the voltage levels of the processing elements (PEs). This reduction in energy consumption comes at the cost of the energy consumption of the level shifters between voltage islands. Moreover, from physical design perspective it is desirable to have a limited number of voltage islands. Considering voltage islanding during mapping of the PEs to the NoC routers can significantly reduce both the computational and the level-shifter energy consumptions and the communication energy consumption on the NoC links. In this paper, we formulate the problem as an optimization problem with an objective of minimizing the overall energy consumption constrained by the performance in terms of delay and the maximum number of voltage islands. We provide the optimal solution to our problem using Mixed Integer Linear Program (MILP) formulation. We also propose a heuristic based on random greedy selection to solve the problem. Experimental results using E3S benchmark applications and some real applications show that the heuristic finds near-optimal solution in almost all cases in a very small fraction of the time required to achieve the optimal solution.
KW - greedy randomized heuristic
KW - integer linear program
KW - multi-processor system-on-chip (MPSoC)
KW - network-on-chip (NoC)
KW - voltage islanding
UR - http://www.scopus.com/inward/record.url?scp=77954695224&partnerID=8YFLogxK
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U2 - 10.1145/1774088.1774197
DO - 10.1145/1774088.1774197
M3 - Conference contribution
AN - SCOPUS:77954695224
SN - 9781605586380
T3 - Proceedings of the ACM Symposium on Applied Computing
SP - 535
EP - 541
BT - APPLIED COMPUTING 2010 - The 25th Annual ACM Symposium on Applied Computing
T2 - 25th Annual ACM Symposium on Applied Computing, SAC 2010
Y2 - 22 March 2010 through 26 March 2010
ER -