Efficient Error Detection for Matrix Multiplication With Systolic Arrays on FPGAs

Fabiano Libano, Paolo Rech, John Brunhaver

Research output: Contribution to journalArticlepeer-review

3 Scopus citations

Abstract

Matrix multiplication has always been a cornerstone in computer science. In fact, linear algebra tools permeate a wide variety of applications: from weather forecasting, to financial market prediction, radio signal processing, computer vision, and more. Since many of the aforementioned applications typically impose strict performance and/or fault tolerance constraints, the demand for fast and reliable matrix multiplication (MxM) is at an all-time high. Typically, increased reliability is achieved through redundancy. However, coarse-grain duplication incurs an often prohibitive overhead, higher than 100%. Thanks to the peculiar characteristics of the MxM algorithm, more efficient algorithm-based hardening solutions have been designed to detect (and even correct) some types of errors with lower overhead. We show that, despite being more efficient, current solutions are still sub-optimal in certain scenarios, particularly when considering persistent faults in Field-Programmable Gate-Arrays (FPGAs). Based on a thorough analysis of the fault model, we propose an error detection technique for MxM that decreases both algorithmic and architectural costs by over a polynomial degree, when compared to existing algorithm-based strategies. Furthermore, we report arithmetic overheads at the application level to be under 1% for three state-of-the-art Convolutional Neural Networks (CNNs).

Original languageEnglish (US)
Pages (from-to)2390-2403
Number of pages14
JournalIEEE Transactions on Computers
Volume72
Issue number8
DOIs
StatePublished - Aug 1 2023
Externally publishedYes

Keywords

  • Error detection
  • FPGA
  • matrix multiplication
  • systolic array

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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