@article{c0574e940d364a0f8e78ea3ab3618272,
title = "DyPO: Dynamic Pareto-optimal configuration selection for heterogeneous MpSoCs",
abstract = "Modern multiprocessor systems-on-chip (MpSoCs) offer tremendous power and performance optimization opportunities by tuning thousands of potential voltage, frequency and core configurations. As the workload phases change at runtime, different configurations may become optimal with respect to power, performance or other metrics. Identifying the optimal configuration at runtime is infeasible due to the large number of workloads and configurations. This paper proposes a novel methodology that can find the Pareto-optimal configurations at runtime as a function of the workload. To achieve this, we perform an extensive offline characterization to find classifiers that map performance counters to optimal configurations. Then, we use these classifiers and performance counters at runtime to choose Pareto-optimal configurations. We evaluate the proposed methodology by maximizing the performance per watt for 18 single- and multi-threaded applications. Our experiments demonstrate an average increase of 93%, 81% and 6% in performance per watt compared to the interactive, ondemand and powersave governors, respectively.",
keywords = "Basic blocks, Clang, DPM, DVFS, Energy, LLVM, Logistic regression, Mobile platforms, Multi-cores, PAPI, Pareto optimization, Performance per watt, Power",
author = "Ujjwal Gupta and Patil, {Chetan Arvind} and Ganapati Bhat and Prabhat Mishra and Umit Ogras",
note = "Funding Information: This article was presented in the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) 2017 and appears as part of the ESWEEK-TECS special issue. This work was supported partially by National Science Foundation (NSF) grants CNS-1526562 and CNS-1526687, and Semiconductor Research Corporation (SRC) task 2721.001. Author{\textquoteright}s addresses: U. Gupta, C. A. Patil, G. Bhat, and U. Y. Ogras, School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ, 85287; emails: {ujjwal, chetanpatil, gmbhat, umit}@asu.edu; P. Mishra, Department of Computer and Information Science and Engineering, University of Florida, Gainsville, FL, 32611; email: prabhat@ufl.edu. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. {\textcopyright} 2017 ACM 1539-9087/2017/09-ART123 $15.00 https://doi.org/10.1145/3126530 Publisher Copyright: {\textcopyright} 2017 ACM.",
year = "2017",
month = sep,
doi = "10.1145/3126530",
language = "English (US)",
volume = "16",
journal = "ACM Transactions on Embedded Computing Systems",
issn = "1539-9087",
publisher = "Association for Computing Machinery (ACM)",
number = "5s",
}