Modern high-performance processors are embedded in portable electronics, such as smartphones, self-driving automobiles, and augmented reality wearable. These computing platforms provide real-time direction navigation, high definition video entertainment, real-time sensing and control. One of the major performance limiting factors in these platforms is the poorly designed thermal solution to prevent overheating at the processor transistor junction and at the platform surface. The former limits the maximum operating temperature of transistors to guarantee reliability and lifetime whereas the latter limits the maximum platform surface temperature to ensure user ergonomic comfort. To design effective cooling solutions for high-performance, multi-layer, multi-processor platforms, an accurate and detailed platform level temperature model is needed. In this work, we present a detailed finite volume model to predict the temperature behavior of a tightly packaged, high-performance portable platform, from the system level down to the processor architecture level. We first characterize the thermal response of real-world, representative mobile workloads and perform parametric studies to predict the processor junction and platform surface temperature based on the properties of the platform. We observe that thermal hot spots are sensitive to workload computation characteristics. In particular, for mobile workloads, such as web browsing, computations often occur in short time burst, leading to instantaneous power spikes. This results in temperature spikes as thermal hot spots. To mitigate the thermal issue, modern systems implement dynamic voltage and frequency scaling during high performance and high power scenario to prevent cores from overheating. We validate the proposed temperature model used to predict the maximum temperature at the processor chip and at the platform surface, with measurements from the embedded temperature sensors and an infrared camera. The temperature prediction accuracy for hot spots on the processor chip and on the platform surface is demonstrated to be higher than 90%. With the tool, we show that the physical construction (such as air gaps and material properties) and the floor plan of the multi-layer platform have a profound effect on the system temperature behavior. As the air gap between the different layers of the computing platform increases, the processor temperature rises significantly. Also there exists an optimal thickness setting of the air gap for platform surface thermal spreading. We hope the detailed characterization results, the developed temperature prediction tool, and the insights presented in the paper can motivate advanced thermal management solution for high-performance embedded platforms in the years to come.