TY - GEN
T1 - Design of a robust, high performance standard cell threshold logic family for DSM technology
AU - Leshner, Samuel
AU - Kulkarni, Niranjan
AU - Vrudhula, Sarma
AU - Berezowski, Krzysztof
PY - 2010
Y1 - 2010
N2 - This paper presents the threshold logic latch (TLL), which provides a high performance, low power alternative to traditional CMOS logic networks. TLL is highly robust, even in deep sub-micron technology nodes. Experimental results obtained from simulation of a commercial 65 nm low power process demonstrate a static noise margin up to an order of magnitude greater than those of existing implementations of threshold logic. Examples of automated synthesis of pipelined multipliers using a combination of standard CMOS and a small number of TLL gates are shown through simulation to improve both area and total power by a factor of up to 1.5 and reduce leakage power by a factor of up to 2.3.
AB - This paper presents the threshold logic latch (TLL), which provides a high performance, low power alternative to traditional CMOS logic networks. TLL is highly robust, even in deep sub-micron technology nodes. Experimental results obtained from simulation of a commercial 65 nm low power process demonstrate a static noise margin up to an order of magnitude greater than those of existing implementations of threshold logic. Examples of automated synthesis of pipelined multipliers using a combination of standard CMOS and a small number of TLL gates are shown through simulation to improve both area and total power by a factor of up to 1.5 and reduce leakage power by a factor of up to 2.3.
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U2 - 10.1109/ICM.2010.5696203
DO - 10.1109/ICM.2010.5696203
M3 - Conference contribution
AN - SCOPUS:79951700852
SN - 9781612841519
T3 - Proceedings of the International Conference on Microelectronics, ICM
SP - 52
EP - 55
BT - 2010 International Conference on Microelectronics, ICM'10
T2 - 2010 International Conference on Microelectronics, ICM'10
Y2 - 19 December 2010 through 22 December 2010
ER -