TY - GEN
T1 - Design Considerations of DSP-based SiC-MOSFET SAPF with 100kHz Sampling and Switching Frequency
AU - Zhang, Yuxiao
AU - Dai, Ke
AU - Xu, Hongwei
AU - Lin, Haitao
AU - Zhang, Debin
AU - Lei, Qin
N1 - Funding Information:
VII. ACKNOWLEDGMENT This work was supported by National Natural Science Foundation of China (51277086)
Publisher Copyright:
© 2019 IEEE.
PY - 2019/9
Y1 - 2019/9
N2 - In this paper, a unique 100kHz sampling and switching frequency shunt active power filter (SAPF), which is based on a dual-core DSP TMS320F28377D, is designed to achieve high control bandwidth for the potential market of wide frequency range harmonic suppression and resonance damping in future more electric aircraft (MEA) or high-speed railway power grid. By rearranging different computation segments, such as analog-to-digital conversion, recursive discrete Fourier transform (RDFT), inner-loop current and outer-loop voltage control, the traditional single pipeline code structure in DSP can be reformed as two parallel running groups. This multitasking strategy provides the proposed SAPF with huge advantages on higher frequency harmonic suppression compared to the mostly commercial SAPF with 10~20kHz switching frequency. Detailed parameter design of LCL filter, DC-side capacitor and deadtime are also presented. A 10kVA prototype utilizing CREE SiC power module CCS050M12CM2 is set up to verify the effectiveness of the proposed SAPF. The results show that the total harmonic distortion can be limited within 5%, which complies with the IEEE power quality standard 519-2014.
AB - In this paper, a unique 100kHz sampling and switching frequency shunt active power filter (SAPF), which is based on a dual-core DSP TMS320F28377D, is designed to achieve high control bandwidth for the potential market of wide frequency range harmonic suppression and resonance damping in future more electric aircraft (MEA) or high-speed railway power grid. By rearranging different computation segments, such as analog-to-digital conversion, recursive discrete Fourier transform (RDFT), inner-loop current and outer-loop voltage control, the traditional single pipeline code structure in DSP can be reformed as two parallel running groups. This multitasking strategy provides the proposed SAPF with huge advantages on higher frequency harmonic suppression compared to the mostly commercial SAPF with 10~20kHz switching frequency. Detailed parameter design of LCL filter, DC-side capacitor and deadtime are also presented. A 10kVA prototype utilizing CREE SiC power module CCS050M12CM2 is set up to verify the effectiveness of the proposed SAPF. The results show that the total harmonic distortion can be limited within 5%, which complies with the IEEE power quality standard 519-2014.
KW - Dual-core system
KW - High bandwidth
KW - Parallel digital signal processing
KW - Shunt active power filter
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U2 - 10.1109/ECCE.2019.8912256
DO - 10.1109/ECCE.2019.8912256
M3 - Conference contribution
AN - SCOPUS:85076751402
T3 - 2019 IEEE Energy Conversion Congress and Exposition, ECCE 2019
SP - 4781
EP - 4788
BT - 2019 IEEE Energy Conversion Congress and Exposition, ECCE 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2019
Y2 - 29 September 2019 through 3 October 2019
ER -