TY - JOUR
T1 - Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
AU - Yang, Jinghua
AU - Dengi, Enis
AU - Vrudhula, Sarma
N1 - Funding Information:
Manuscript received August 30, 2017; revised December 29, 2017; accepted February 18, 2018. Date of publication March 22, 2018; date of current version November 30, 2018. This work was supported in part by NSF under Grant 1230401, Grant 1237856, and Grant 1701241 and in part by the NSF IUCRC Center for Embedded Systems. (Corresponding author: Sarma Vrudhula.) The authors are with the School of CIDSE, Arizona State University, Tempe, AZ 85281 USA (e-mail: Jinghua.Yang@asu.edu; Aykut.Dengi@asu.edu; vrudhula@asu.edu).
Publisher Copyright:
© 1993-2012 IEEE.
PY - 2018/12
Y1 - 2018/12
N2 - Systems powered by harvested energy must consume very low power and withstand frequent interruptions in power. Nonvolatile logic (NVL) addresses the latter by saving the system state in flipflops enhanced with spin-transfer torque magnetic tunnel junctions (STT-MTJs) as the nonvolatile storage devices. Manufacturing variations in the STT-MTJs and in CMOS transistors significantly reduce yield, leading to overdesign and high-energy consumption. A detailed analysis of the design tradeoffs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Next, efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5 × more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. Also included are the energy consumption of the proposed NVFF designs when used in two larger function blocks. Experimental results were based on a commercial 40-nm process design kit, and HSPICE simulations with foundry supplied statistical models and data.
AB - Systems powered by harvested energy must consume very low power and withstand frequent interruptions in power. Nonvolatile logic (NVL) addresses the latter by saving the system state in flipflops enhanced with spin-transfer torque magnetic tunnel junctions (STT-MTJs) as the nonvolatile storage devices. Manufacturing variations in the STT-MTJs and in CMOS transistors significantly reduce yield, leading to overdesign and high-energy consumption. A detailed analysis of the design tradeoffs in the driver circuitry for performing backup and restore, and a novel method to design the energy optimal driver for a given yield is presented. Next, efficient designs of two nonvolatile flip-flop (NVFF) circuits are presented, in which the backup time is determined on a per-chip basis, resulting in minimizing the energy wastage and satisfying the yield constraint. To achieve a yield of 98%, the conventional approach would have to expend nearly 5 × more energy than the minimum required, whereas the proposed tunable approach expends only 26% more energy than the minimum. Also included are the energy consumption of the proposed NVFF designs when used in two larger function blocks. Experimental results were based on a commercial 40-nm process design kit, and HSPICE simulations with foundry supplied statistical models and data.
KW - Energy harvesting
KW - Internet of Things (IoT)
KW - flip-flop
KW - low power
KW - magnetic tunnel junction (MTJ)
KW - nonvolatile logic (NVL)
KW - nonvolatile memory (NVM)
KW - resistive random access memory
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U2 - 10.1109/TVLSI.2018.2812700
DO - 10.1109/TVLSI.2018.2812700
M3 - Article
AN - SCOPUS:85044358686
SN - 1063-8210
VL - 26
SP - 2628
EP - 2640
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 12
M1 - 8322451
ER -