Design and management of voltage-frequency island partitioned networks-on-chip

Umit Y. Ogras, Radu Marculescu, Diana Marculescu, Eun Gu Jung

Research output: Contribution to journalArticlepeer-review

118 Scopus citations


The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of our approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an field-programmable gate-array (FPGA) prototype for an NoC with multiple VFIs.

Original languageEnglish (US)
Article number4804129
Pages (from-to)330-341
Number of pages12
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
StatePublished - Mar 2009
Externally publishedYes


  • Energy and power consumption
  • Multiprocessor systems-on-chip (MPSoCs)
  • Networks-on-chip (NoCs)
  • Voltage-frequency islands (VFIs)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Design and management of voltage-frequency island partitioned networks-on-chip'. Together they form a unique fingerprint.

Cite this