TY - JOUR
T1 - Design and management of voltage-frequency island partitioned networks-on-chip
AU - Ogras, Umit Y.
AU - Marculescu, Radu
AU - Marculescu, Diana
AU - Jung, Eun Gu
N1 - Funding Information:
Manuscript received December 10, 2007; revised April 21, 2008. Current version published February 19, 2009. Preliminary results of this work appeared in the Proceedings of Design Automation Conference, Anaheim, CA, June 2008. This research was supported in part by SRC under Contract GRC 2008 HJ 1800, Marco Gigascale Systems Research Center (GSRC) one of the five research centers funded under the Focus Center Research Program, a Semiconductor Research Corporation program, and in part by NSF Grant CNS-0720529 and NSF Grant CCF-0702420. The work of E. G. Jung was supported by the Korea Research Foundation Grant funded by the Korean Government (MOEHRD) (KRF-2006-352-D00146).
PY - 2009/3
Y1 - 2009/3
N2 - The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of our approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an field-programmable gate-array (FPGA) prototype for an NoC with multiple VFIs.
AB - The design of many core systems-on-chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, we consider network-on-chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for runtime energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of our approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an field-programmable gate-array (FPGA) prototype for an NoC with multiple VFIs.
KW - Energy and power consumption
KW - Multiprocessor systems-on-chip (MPSoCs)
KW - Networks-on-chip (NoCs)
KW - Voltage-frequency islands (VFIs)
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U2 - 10.1109/TVLSI.2008.2011229
DO - 10.1109/TVLSI.2008.2011229
M3 - Article
AN - SCOPUS:63149129753
SN - 1063-8210
VL - 17
SP - 330
EP - 341
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 3
M1 - 4804129
ER -