Abstract
Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but are not suited to small fast memories such as first level caches, due to the area and speed penalties they entail. Here, an error detection and correction scheme that is appropriate for use in low latency first level caches and other small, fast memories such as register files is presented. The scheme allows fine, e.g., byte write granularity with acceptable storage overhead. Analysis demonstrates that the proposed method provides adequate soft error rate reduction with improved latency and area cost.
Original language | English (US) |
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Title of host publication | IEEE International Conference on Computer Design, ICCD 2006 |
Pages | 88-92 |
Number of pages | 5 |
DOIs | |
State | Published - 2006 |
Event | 24th International Conference on Computer Design 2006, ICCD - San Jose, CA, United States Duration: Oct 1 2006 → Oct 4 2006 |
Other
Other | 24th International Conference on Computer Design 2006, ICCD |
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Country/Territory | United States |
City | San Jose, CA |
Period | 10/1/06 → 10/4/06 |
Keywords
- Error correcting codes
- Error detection and correction
- Memory soft errors
ASJC Scopus subject areas
- Computer Graphics and Computer-Aided Design
- Software