TY - GEN
T1 - Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access
AU - Kim, Minkyu
AU - Seo, Jae Sun
N1 - Funding Information:
ACKNOWLEDGEMENT This work was in part supported by NSF grant 1652866, Samsung Electronics, and C-BRIC, one of six centers in JUMP, a SRC program sponsored by DARPA.
Publisher Copyright:
© 2020 IEEE.
PY - 2020/3
Y1 - 2020/3
N2 - This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by 2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.
AB - This paper presents an ASIC accelerator for deep convolutional neural networks (DCNNs) featuring a novel conditional computing scheme that synergistically combines precision-cascading with zero-skipping. To reduce many redundant convolution operations that are followed by max-pooling operations, we propose precision-cascading, where the input features are divided into a number of low-precision groups and approximate convolutions with only the most significant bits (MSBs) are performed first. Based on this approximate computation, the full-precision convolution is performed only on the maximum pooling output that is found. This way, the total number of bit-wise convolutions can be reduced by 2× without affecting the output feature values and with <0.8% degradation in final ImageNet classification accuracy. Precision-cascading provides the added benefit of increased sparsity per low-precision group, which we exploit with zero-skipping to eliminate clock cycles as well as external memory access that involve zero inputs. By jointly optimizing the conditional computing scheme and hardware architecture, the 40nm prototype chip demonstrates a peak energy-efficiency of 8.85 TOPS/W at 0.9V supply and low external memory access of 55.31 MB (or 0.0018 access/MAC) for ImageNet classification with VGG-16 CNN.
KW - ASIC
KW - Deep convolutional neural networks (DCNNs)
KW - conditional computing
KW - deep learning
KW - energy-efficient accelerator
UR - http://www.scopus.com/inward/record.url?scp=85084506452&partnerID=8YFLogxK
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U2 - 10.1109/CICC48029.2020.9075931
DO - 10.1109/CICC48029.2020.9075931
M3 - Conference contribution
AN - SCOPUS:85084506452
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2020 IEEE Custom Integrated Circuits Conference, CICC 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2020 IEEE Custom Integrated Circuits Conference, CICC 2020
Y2 - 22 March 2020 through 25 March 2020
ER -