Data memory design and exploration for low-power embedded systems

Wen Tsong Shiue, Sathishkumar Udayanarayanan, Chaitali Chakrabarti

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration procedure based on three performance metrics, namely, cache size, the memory access time and the energy consumption. We show the importance of including energy in the performance metrics, since an increase in the cache size and line size reduces the memory access time but does not necessarily reduce the energy consumption. The memory exploration procedures enable us to find the cache configuration (cache size, line size) that satisfies the area and time constraints while minimizing the energy consumption, and the cache configuration that satisfies the area and energy constraints while minimizing the memory access time. The exploration procedures for cache configuration is very efficient since it considers only a selected set of candidate points. Finally, we validate our exploration procedures by running simulation experiments on MediaBench applications.

Original languageEnglish (US)
Pages (from-to)553-568
Number of pages16
JournalACM Transactions on Design Automation of Electronic Systems
Issue number4
StatePublished - 2001


  • Data cache
  • Memory
  • Search space pruning

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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