Cross-layer modeling and simulation of circuit reliability

Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze

Research output: Contribution to journalArticlepeer-review

48 Scopus citations


Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

Original languageEnglish (US)
Article number6685855
Pages (from-to)8-23
Number of pages16
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number1
StatePublished - Jan 2014


  • Bias temperature instability
  • Circuit simulation
  • Integrated circuit reliability
  • Reliability modeling

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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