Process simulation is particularly appropriate to production control in CMOS IC fabrication. The process complexity and the divergent characteristics of the two transistor types make optimisation of their performance difficult. Simulation provides a fast route to test compromises in process specifications. This paper presents a process simulation of small geometry (2 mu m) CMOS devices. Previous studies on narrow width effects in MOS transistors have concentrated on NMOS or N-well CMOS technologies. The present work concentrates specifically on width effects in a P-well CMOS process where diffusion of both the field implant and the P-well must be modelled during field oxidation. The simulation results allow the effective channel width of the MOS transistor to be determined.
|Original language||English (US)|
|Title of host publication||Unknown Host Publication Title|
|Number of pages||10|
|State||Published - Dec 1 1984|
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