TY - GEN
T1 - Constrained worst case loads for microprocessors
AU - Lambert, W. J.
AU - Ayyanar, Raja
PY - 2008
Y1 - 2008
N2 - The risk of a microprocessor execution error increases as the voltage at the die decreases, making worst case analysis of the die voltage a good metric for microprocessor voltage regulation performance. However, the actual worst case load is unlikely to ever occur. This paper derives the results for the worst case load from linear system theory, and then uses a constrained optimization problem to calculate the worst case load under more probable circumstances, demonstrating that loads with much higher likelihood of occurrence can cause voltages at the die nearly as low as the worst case.
AB - The risk of a microprocessor execution error increases as the voltage at the die decreases, making worst case analysis of the die voltage a good metric for microprocessor voltage regulation performance. However, the actual worst case load is unlikely to ever occur. This paper derives the results for the worst case load from linear system theory, and then uses a constrained optimization problem to calculate the worst case load under more probable circumstances, demonstrating that loads with much higher likelihood of occurrence can cause voltages at the die nearly as low as the worst case.
UR - http://www.scopus.com/inward/record.url?scp=49249092604&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=49249092604&partnerID=8YFLogxK
U2 - 10.1109/APEC.2008.4522853
DO - 10.1109/APEC.2008.4522853
M3 - Conference contribution
AN - SCOPUS:49249092604
SN - 9781424418749
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 1061
EP - 1066
BT - 2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
T2 - 2008 23rd Annual IEEE Applied Power Electronics Conference and Exposition, APEC
Y2 - 24 February 2008 through 28 February 2008
ER -