TY - GEN
T1 - Computation of joint timing yield of sequential networks considering process variations
AU - Goel, Amit
AU - Bhardwaj, Sarvesh
AU - Ghanta, Praveen
AU - Vrudhula, Sarma
PY - 2007
Y1 - 2007
N2 - This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400 × compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.
AB - This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400 × compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.
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U2 - 10.1007/978-3-540-74442-9_13
DO - 10.1007/978-3-540-74442-9_13
M3 - Conference contribution
AN - SCOPUS:37849026136
SN - 9783540744412
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 125
EP - 137
BT - Integrated Circuit and System Design
PB - Springer Verlag
T2 - 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2007
Y2 - 3 September 2007 through 5 September 2007
ER -