Circuit-level impact of a-Si:H thin-film-transistor degradation effects

David Allee, Lawrence T. Clark, Bryan D. Vogt, Rahul Shringarpure, Sameer M. Venugopal, Shrinivas Gopalan Uppili, Korhan Kaftanoglu, Hemanth Shivalingaiah, Zi P. Li, J. J Ravindra Fernando, Edward J. Bawolek, Shawn M. O'Rourke

Research output: Contribution to journalReview articlepeer-review

52 Scopus citations


This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Original languageEnglish (US)
Pages (from-to)1166-1176
Number of pages11
JournalIEEE Transactions on Electron Devices
Issue number6
StatePublished - 2009


  • Amorphous silicon
  • Flexible electronics
  • Thin-film transistors (TFTs)
  • Threshold-voltage shift

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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