We present Chameleon, an architecture for neural network training and inference design exploration on FPGAs. While there exists a great number of different network types and optimizations, it is not always clear how these differences impact the hardware implementation of neural networks. Chameleon is created with extensibility and experimentation in mind, supporting a number of activations, neuron types, and signal bitwidths. Furthermore, Chameleon is created to be modular, allowing designers to easily swap existing parts for improved ones, speeding up research iteration. While there exists a large number of inference architectures, we focus on speeding up training, as training time is the bottleneck for neural network architecture exploration. Chameleon therefore aims to help researchers better understand the bottlenecks in training deep neural networks and create models that circumvent these barriers. Finally, Chameleon is designed to be simple, without requiring a compiler or reconfiguration to function. This allows quick localized changes to the architecture and facilitates design exploration. We present synthesis results on an Altera Cyclone V SoC and show the design resource usage. We finish with an evaluation by training a network on the Wisconsin Breast Cancer dataset. The RTL and synthesis files for the architecture will be open-sourced upon publication at http://ascslab.org/research/abc/chameleon/index.html.