Carrier transport in nanodevices

David K. Ferry, Richard Akis, Sujeeth Udipi, Dragica Vasileska, David P. Pivin, Kevin M. Connolly, Jonathan P. Bird, Koji Ishibashi, Yoshinobu Aoyagi, Takuo Sugano, Yuichi Ochiai

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


Future VLSI scaling realization of gate lengths is expected to 70 nm and below. While we do not know all the underlying physics, we are beginning to understand some limiting factors, which include quantum transport, in these structures. The discrete nature of impurities, the fact that devices have critical lengths comparable to their coherence lengths, and size quantization will all be important in these structures. These phenomena will lead to pockets of charge, which will appear as coupled quantum dots in the device transport. We review some of the physics of these dots.

Original languageEnglish (US)
Pages (from-to)1841-1845
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number3 SUPPL. B
StatePublished - Mar 1997


  • Device modeling
  • Device physics
  • Inhomgeneities
  • Quantum dots
  • Quantum transport
  • Random impurities

ASJC Scopus subject areas

  • General Engineering
  • General Physics and Astronomy


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