Automated techniques for synthesis of application-specific network-on-chip architectures

This paper addresses the automated synthesis of a custom network-on-chip architecture whose topology is optimized for the specific communication requirements of the target device. The optimization objectives include power consumption and resource usage. This paper presents a two-stage synthesis approach consisting of the following: 1) core to router mapping and 2) custom topology and route generation. In particular, it presents an optimal technique for core to router mapping [stage 1)] and a factor-2 approximation algorithm for custom topology generation [stage 2)]. The superior quality of the techniques is established by experimentation with benchmark applications and by comparisons with existing approaches.