Associative Processor Architecture—a Survey

S. S. Yau, H. S. Fung

Research output: Contribution to journalArticlepeer-review

53 Scopus citations


A survey of the architecture of various associative processors is presented with emphasis on their characteristics, categorization, and implementation, and especially on recent developments. Based on their architecture, associative processors are classified into four categories, namely fully parallel, bit-serial, word-serial and block-oriented. The fully parallel associative processors are divided into two classes, word-orgamzed and distributed logic associative processors.

Original languageEnglish (US)
Pages (from-to)3-27
Number of pages25
JournalACM Computing Surveys (CSUR)
Issue number1
StatePublished - Mar 1 1977
Externally publishedYes


  • Associative processors
  • bit-serial
  • block-ormnted
  • categomzation
  • computer architecture
  • distributed logic
  • fully parallel
  • hardware
  • implementation
  • large-scale integration
  • word-serial

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)


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