Associative memory architecture for video compression

F. Idris, S. Panchanathan

Research output: Contribution to journalConference articlepeer-review


In this paper, we propose an unified associative memory architecture for real-time implementation of motion estimation and frame adaptive vector quantization for video compression. The proposed architecture has the advantages of simplicity, partitionability, and modularity and has hence the potential for VLSI implementation.

Original languageEnglish (US)
Pages (from-to)93-96
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
StatePublished - Dec 1 1994
Externally publishedYes
EventProceedings of the 1994 IEEE International Symposium on Circuits and Systems. Part 3 (of 6) - London, England
Duration: May 30 1994Jun 2 1994

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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