TY - GEN
T1 - Application specific networks-on-chip synthesis
T2 - 17th IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
AU - Kashi, Somayeh
AU - Patooghy, Ahmad
AU - Rahmatiy, Dara
AU - Fazeli, Mahdi
AU - Kinsy, Michel A.
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/8/7
Y1 - 2018/8/7
N2 - Multiple Voltage Supply (MSV) chip fabrication is considered as a viable technique to address the power and thermal challenges of modern many-core systems. Efficiency of this technique has been demonstrated in application specific Network-on-Chips (NoCs) which have lots of cores and various operating voltages/frequencies. In this paper, a fourphase synthesis toolchain is proposed and evaluated for the design of multi-voltage application specific NoCs. The proposed synthesis toolchain performs i) core to router allocation, ii) voltage islanding to match voltages of cores connected to the same router, iii) hierarchical floorplanning to reduce the complexity of power delivery network, and iv) path allocation to connect routers based on the application requirements. The distinguishing feature of the proposed toolchain is that, for the first time, it performs the router allocation phase prior to voltage islanding. This offers more flexibility and more efficiency in the multi-voltage NoC synthesis. Experimental results on real world benchmarks show that the proposed toolchain provides 63% less energy consumption as well as more than double the design alternatives satisfying the benchmarks requirements compared to existing approaches.
AB - Multiple Voltage Supply (MSV) chip fabrication is considered as a viable technique to address the power and thermal challenges of modern many-core systems. Efficiency of this technique has been demonstrated in application specific Network-on-Chips (NoCs) which have lots of cores and various operating voltages/frequencies. In this paper, a fourphase synthesis toolchain is proposed and evaluated for the design of multi-voltage application specific NoCs. The proposed synthesis toolchain performs i) core to router allocation, ii) voltage islanding to match voltages of cores connected to the same router, iii) hierarchical floorplanning to reduce the complexity of power delivery network, and iv) path allocation to connect routers based on the application requirements. The distinguishing feature of the proposed toolchain is that, for the first time, it performs the router allocation phase prior to voltage islanding. This offers more flexibility and more efficiency in the multi-voltage NoC synthesis. Experimental results on real world benchmarks show that the proposed toolchain provides 63% less energy consumption as well as more than double the design alternatives satisfying the benchmarks requirements compared to existing approaches.
KW - Application-specific chip
KW - Custom NoC synthesis
KW - Floorplanning
KW - Islanding
KW - Partitioning
UR - http://www.scopus.com/inward/record.url?scp=85052129802&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85052129802&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2018.00020
DO - 10.1109/ISVLSI.2018.00020
M3 - Conference contribution
AN - SCOPUS:85052129802
SN - 9781538670996
T3 - Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI
SP - 52
EP - 57
BT - Proceedings - 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018
PB - IEEE Computer Society
Y2 - 9 July 2018 through 11 July 2018
ER -