TY - GEN
T1 - Application specific network-on-chip design with guaranteed quality approximation algorithms
AU - Srinivasan, Krishnan
AU - Chatha, Karam S.
AU - Konjevod, Goran
PY - 2007
Y1 - 2007
N2 - Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with integer linear programming (ILP) formulations, and heuristic techniques.
AB - Network-on-Chip (NoC) architectures with optimized topologies have been shown to be superior to regular architectures (such as mesh) for application specific multiprocessor System-on-Chip (MPSoC) devices. The application specific NoC design problem takes as input the system-level floorplan of the computation architecture, characterized library of NoC components, and the communication performance requirements. The objective is to generate an optimized NoC topology, and routes for the communication traces on the architecture such that the performance requirements are satisfied and power consumption is minimized. The paper discusses a two stage automated approach consisting of i) core to router mapping, and ii) topology and route generation for design of custom NoC architectures. In particular it presents an optimal technique for core to router mapping (stage i), and a factor 2 approximation algorithm for custom topology generation (stage ii). The superior quality of the techniques is established by experimentation with benchmark applications, and comparisons with integer linear programming (ILP) formulations, and heuristic techniques.
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U2 - 10.1109/ASPDAC.2007.357983
DO - 10.1109/ASPDAC.2007.357983
M3 - Conference contribution
AN - SCOPUS:46649116535
SN - 1424406293
SN - 9781424406296
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 184
EP - 190
BT - Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
T2 - ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
Y2 - 23 January 2007 through 27 January 2007
ER -