Analysis of STT-RAM cell design with multiple MTJs per access

Henry Park; Richard Dorrance; Amr Amin; Fengbo Ren; Dejan Marković; C. K. Ken Yang

doi:10.1109/NANOARCH.2011.5941483

Analysis of STT-RAM cell design with multiple MTJs per access

Henry Park, Richard Dorrance, Amr Amin, Fengbo Ren, Dejan Marković, C. K. Ken Yang

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cell's access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.

Original language	English (US)
Title of host publication	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Pages	53-58
Number of pages	6
DOIs	https://doi.org/10.1109/NANOARCH.2011.5941483
State	Published - 2011
Externally published	Yes
Event	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 - San Diego, CA, United States Duration: Jun 8 2011 → Jun 9 2011

Publication series

Name	Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011

Other

Other	2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011
Country/Territory	United States
City	San Diego, CA
Period	6/8/11 → 6/9/11

Keywords

1T-3MTJ
Magnetic Tunnel Junction
STT-RAM

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/NANOARCH.2011.5941483

Cite this

Park, H., Dorrance, R., Amin, A., Ren, F., Marković, D., & Ken Yang, C. K. (2011). Analysis of STT-RAM cell design with multiple MTJs per access. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011 (pp. 53-58). Article 5941483 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). https://doi.org/10.1109/NANOARCH.2011.5941483

Analysis of STT-RAM cell design with multiple MTJs per access. / Park, Henry; Dorrance, Richard; Amin, Amr et al.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 53-58 5941483 (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Park, H, Dorrance, R, Amin, A, Ren, F, Marković, D & Ken Yang, CK 2011, Analysis of STT-RAM cell design with multiple MTJs per access. in Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011., 5941483, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, pp. 53-58, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, San Diego, CA, United States, 6/8/11. https://doi.org/10.1109/NANOARCH.2011.5941483

Park H, Dorrance R, Amin A, Ren F, Marković D, Ken Yang CK. Analysis of STT-RAM cell design with multiple MTJs per access. In Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011. 2011. p. 53-58. 5941483. (Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011). doi: 10.1109/NANOARCH.2011.5941483

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Analysis of STT-RAM cell design with multiple MTJs per access

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Keywords

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