An analytical approach for network-on-chip performance analysis

Umit Y. Ogras, Paul Bogdan, Radu Marculescu

Research output: Contribution to journalArticlepeer-review

108 Scopus citations


Networks-on-chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. In this paper, we present a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The proposed model can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.

Original languageEnglish (US)
Article number5621037
Pages (from-to)2001-2013
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
StatePublished - Dec 2010
Externally publishedYes


  • Multiprocessor systems-on-chip (MPSoCs)
  • networks-on-chip (NoCs)
  • performance analysis

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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